Andrea Giannini

Digital/RTL Design

The reason I joined Fathom Computing goes back to the history of computers and to the issues that integrated circuits (ICs) are facing today. With the end of the Dennard scaling that allowed the IC power density to remain roughly constant with the shrinking in size of transistors, power consumption has become the main bottleneck of modern computer architectures, limiting the increase performance trend of modern processors from a 50% per year to a 3% per year. That being said, energy efficiency (performance/power) has become a critical issue in modern designs.

One trend to improve the energy efficiency when accessing data is to store everything on the on-chip SRAMs and use as much data re-use as possible. Of course this cannot be done for massive NN workloads since the die area is limited by the amount of defects caused by the fabrication process (larger dies implies lower yield). In other words, when faced with the challenge of heavily increasing performances on AI workloads, we are forced by the current die area/yield trade-off to a multi-dies system connected with advanced networking schemes.

What if there is a way to store all data on-chip, without increasing die area? Connecting multiple ICs with very high energy efficiency during communication would be equivalent to having a large die area and a high process yield! In this seemingly ideal world we could use as many SRAMs chips as we want to fulfill all the memory (and compute) requirements we need. One more time computer architects are "[...] faced with a series of great opportunities - brilliantly disguised as insoluble problems" (John W. Gardner).

At Fathom we tackle directly the scaling of multi-dies interconnection, opening the doors for new possibilities in the world of computer designs. Thanks to what we are developing, long-range energy dissipation is not anymore a problem. The energy efficiency when communicating off-chip is becoming close to the energy-efficiency of local on-chip interconnections. An array of separate ICs can be abstracted as a single large Domain Specific Architecture (DSA) without compromising die area for process yield, reducing the power density requirements for a given performance target or increasing the potential performance achievable for a given power density budget. Thanks to our custom optical system we can connect together common 2D ICs in an hyperdimensional space, exploiting the best of both worlds: computing in advanced technology nodes, while interconnecting chips with free space optics, with high connection density and extremely low energy per bit.

The thrill of working on complex challenges in computer design, together with the opportunities to overcome the barriers imposed by standard IC designs in an open-minded and multi-disciplinary environment convinced me to start my journey in Fathom Computing.